1. Field of the Invention
The invention relates generally to a component of an integrated circuit protected against random logic events and an associated method of manufacture. The component may be a storage cell, for example, a multipoint memory cell, a latch, RS or flip-flop type trigger circuit or an SRAM cell. The component may also be logic circuit, for example, a combinatorial logic circuit or a dynamic logic circuit.
Embodiments of the invention is particularly useful for the making of electronic devices whose components are designed with dimensions smaller than 0.25 μm.
2. Description of the Prior Art
The constant and gradual miniaturization of electronic circuits is giving rise to increasingly efficient and ever smaller circuits. This means, however, that the circuits are becoming increasingly sensitive to their external environment and especially to random logic events caused by an additional supply of energy from outside the circuit.
A random logic event is a momentary change in state or a transient state (voltage and/or current spike) at a point of an integrated circuit. By definition, a random event is unpredictable or barely predictable. Random logic events may have different origins. The consequences of a random logic event may be varied and their importance may be variable. In a memory, for example, a random logic event gives rise to a change in the contents of a memory cell which will have to be reprogrammed to recover its initial value.
A random logic event is induced, for example, by the impinging of a charged energy particle on a point of an integrated circuit. A random factor of this type is known as a “single event upset” or SEU.
This type of random factor was previously encountered in the context of outer-space applications where ionizing radiation is a major factor in the operation of integrated circuits. In civilian or terrestrial applications, the effects of ionizing radiation have hitherto been overlooked. This is no longer the case for integrated circuits whose components have dimensions smaller than 0.5 micrometers because the circuits become increasingly sensitive as their dimensions decrease.
A random logic event may also be induced by localized capacitive coupling between two layers of one and the same integrated circuit. The commonly used term here is “glitch” or “single event transient” (SET).
The impinging of an energy particle or the capacitive coupling between two layers gives rise to an addition of charge to the circuit. This generally results in a voltage or current spike at a point of the circuit (impact point in the case of an SEU, or a coupling point in the case of a glitch). The current or voltage variation is generally very brief. Its duration typically ranges from a few picoseconds to a few hundred picoseconds.
The current or voltage variation may have no effect on the circuit. However, it may give rise to a random logic event if the added charge is greater than the critical charge of the circuit.
The critical charge of a circuit is the minimum charge that must be added for a random logic event to appear, a random logic event being a change in logic state at a point of the circuit. The critical charge of a circuit is especially small as the technology used to make it is small. The circuits made in the smallest technologies (0.25 μm, 0.13 μm) are thus particularly sensitive to random events.
A bistable circuit is generally formed (FIG. 1) by two inverters 110, 120 connected head-to-tail. An input of the first inverter 110 and an output of the second inverter 120 constitute a first input point A of the bistable circuit. An output of the inverter 110 and an input of the inverter 120 constitute a second input point B of the bistable circuit.
The inverter 110, in a known way, comprises a P type transistor 112 and an N type transistor 114 connected in series; a first supply voltage VDD is applied to the source of the P type transistor and a second supply voltage (most usually a ground GND of the circuit) is applied to the source of the N type transistor, the drains of the two transistors are connected together to an output of the inverter 110 and the gates of the two transistors are connected together to an input of the inverter 110. The inverter 120 is made identically with two transistors 122, 124.
A bistable circuit of this kind is, for example, used for the making of a storage cell for a SRAM (also called a six-transistor cell). A cell of this kind comprises a bistable circuit (inverters 110, 120) and two access transistors 130, 140 (shown in dashes in FIG. 1) whose drains are connected respectively to the inputs/outputs A, B of the bistable circuit. The gates of the transistors 130, 140 are connected together to a common word line (FIG. 1). The source of the transistor 130 is connected to a bit line BIT-A and the source of the transistor 140 is connected to a bit line BIT-B.
The FIGS. 2, 3 are respectively a view in perspective and a top view of a known implementation of a six-transistor storage cell, which is made as follows on a P-type substrate comprising an N-type well.
First of all, the following diffusion zones are made at a first level: a diffusion zone 210 forming the drain/source channel of the P-type transistor 112, a diffusion zone 212 forming the channel of the P-type transistor 122, a diffusion zone 214 forming the channel of the N-type transistor 124 and the channel of the N-type access transistor 130, and a diffusion zone 216 forming the channel of the N-type transistor 114 and the channel of the N-type access transistor 140.
Then polysilicon zones are made at a second level: a zone 220 forming the common gate of the transistors 112, 114, a zone 222 forming the common gate of the transistors 122, 124, and two zones 224, 226 respectively forming the gates of the access transistors 130, 140.
Contacts (shown in the form of vertical bars in FIGS. 2, 3) and a first metal level M1 are then made to connect the different zones appropriately. A metal zone M1 230 is thus connected firstly to the polysilicon zone 220 by the contact 260 and, secondly, to the diffusion zones 212, 214 by the contacts 252, 250. Similarly, a metal zone M1 232 is connected to the polysilicon zone 222 by the contact 272 and to the diffusion zones 210, 216 by the contacts 256, 258. The metal zones 230, 232 in practice form the inputs/outputs A, B of the bistable circuit. Other metal zones M1 are added, firstly to connect the gates and the sources of the access transistors 130, 140 (zones M1 234, 238, 236, 240 and associated contacts 255, 263, 254, 262) or to power the sources of the transistors 112, 114, 122, 124 (zones M1 244, 246, 248, 242 and associated contacts).
Any component of an integrated circuit made by the smallest technologies is sensitive to random logic events. This is the case of a bistable circuit or any component comprising at least one bistable circuit: latch, RS or flip-flop type circuit, SRAM type memory cell, multipoint memory cell, etc. This is also the case with any dynamic logic circuit or any combinatorial logic circuit.
One solution to the problem of protecting a circuit against random events consists of increasing its critical charge.
The document “A Novel 0.20 mm. Full CMOS SRAM Cell Using Stacked Cross Couple with Enhanced Soft Error Immunity”, Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International, pages 205–209, 6–9 Dec. 1998 (hereinafter D1) shows that it is possible to protect a SRAM cell by adding a capacitor between the two inputs/outputs A, B, of the cell. The added capacitor has the advantage of increasing the critical charge of the memory cell which thus becomes less sensitive to random logic events.
According to D1, the added capacitor is connected between the two inputs/outputs A, B of the memory cell (FIG. 3 of D1). More specifically, the contact zone of the P-type transistor and of the N-type transistor of each inverter 110, 120 constitutes an electrode of the added capacitor.
According to D1, as compared with the process of manufacture of an unprotected memory cell, three additional process steps are needed to make the capacitor (FIGS. 6a to 6d of D1): the deposition of a TiN layer to form a first electrode of the capacitor, the deposition of a SiN layer to form the insulator of the capacitor, then the deposition of a TiN to form the second electrode of the capacitor. Thus a “stacked cross couple” is obtained.
One drawback of the storage cell of D1 is its dissymmetry, which favors one logic state of the cell rather than another.
Yet another drawback of the cell of D1 is the fact that, in setting the size of the capacitor its critical charge is fixed when it is being designed. It cannot be modified according to the conditions of use of the cell, depending, for example, on the medium in which the cell is used.
Applied to any other component (latches, logic circuits, etc.), the solution of D1 has the same advantages and the same drawbacks.